1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a semiconductor device having an ECC circuit which corrects an error in output data from a memory.
2. Description of the Related Art
The operation speed of semiconductor devices is enhanced more and more and the integration density of elements of the devices is also extremely enhanced with the development of the semiconductor device technology. As a result, an influence by not only the degradation-fault but also the delay-fault as the fault mode of the device increases and a serious problem occurs. Therefore, the actual speed test, that is, at-speed test in the initial stage of the device manufacturing process becomes important. Particularly, a memory in the chip acts as a critical path of the whole chip in many cases, and therefore, a self-test circuit called a BIST (Built-In-Self Test) circuit is mounted on the chip and the at-speed test for the memory is made in the wafer stage.
The capacity of storage nodes of cells configuring the memory is reduced with shrinkage of elements, and therefore, a soft error of the memory develops into a major problem. As a measure to prevent occurrence of the soft error, an ECC (Error Correcting Code) circuit is mounted on the memory in the chip in many cases. The memory having the ECC circuit mounted thereon stores code bits for testing in addition to normal data bits. The ECC circuit detects the presence or absence of an error in the data bits based on the value of the code bits, detects one of the bits in which the error occurs, corrects the error and outputs the corrected bits to the exterior. The number of error bits in the same word which can be corrected is determined according to a code used by the ECC circuit. Generally, a one-bit error correction code or a SEC-DED code which is capable of performing a single error correction and two or more error detection is often used.
The block configuration of a conventional memory device used when the memory having the ECC circuit mounted thereon is tested by use of a BIST circuit is shown in FIG. 10. In FIG. 10, a BIST circuit 91 checks data output via an ECC circuit 92 and determines whether or not an error is present in output data of a memory array 93. However, in the memory device having the ECC circuit 92 mounted thereon, a larger number of operation processes are performed in a case wherein an error has occurred than in a case wherein no error has occurred. Therefore, a critical path of the memory operation often occurs when an error correction is made.
However, since the frequency of occurrence of soft errors is extremely low, the critical path hardly appears at the time of at-speed test. Therefore, in this case, the critical path is not dealt with as an object of the at-speed test.
For example, in Jap. Pat. Appln. KOKAI Publication Disclosure No. 2003-36697, a test circuit for a semiconductor memory is disclosed. The test circuit has a pseudo error signal generating circuit between a memory circuit and a BIST circuit, converts output data from the memory circuit according to a set signal and generates a pseudo error signal necessary for checking the operation of the BIST circuit.
However, since no ECC circuit is provided in the test circuit of the semiconductor memory disclosed in this Jap. Pat. Appln. KOKAI Publication Disclosure No. 2003-36697, no measure to cope with a soft error of the memory is taken.